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ZMD44101
Single-Chip 868MHz to 928MHz RF Transceiver
Introduction
Key Features
IEEE 802.15.4 compliant ISM band transceiver with RF and baseband Direct Sequence Spread Spectrum (DSSS) Burst data rate 20kbit/s (EU), 40kbit/s (US) Transmit range up to 100 meter (LoS) Low power for battery operated devices SPI and Parallel interfaces Compliant PHY and Thin MAC Available in 48-lead QFN (7mm X 7mm) package
Description
The ZMD44101 is a fully integrated system-on-chip CMOS transceiver, providing license free multichannel operation in the 868.3MHz (EU) and 902MHz to 928MHz (US) ISM bands. The low power baseband transceiver is optimized for data rates up to 40kbp/s and incorporates direct sequence spread spectrum technology to assure reliable data transfer in hostile RF environments. The high level of integration, shown below, includes a thin Media Access Controller, resulting in a minimum of external components and lower application costs.
Operating Reference Data
Temperature Range................-40C to +85C Supply Voltage, VDD............................+2.4 V Typical Supply Current (Tx active)...........32mA Typical Supply Current (Rx active)...........28mA Typical Supply Current (sleep mode)...........2A Frequency Range.............868MHz to 928MHz
Applications
Energy Management Remote Metering and Control Home and Building Control Industrial Networks Remote Keyless Entry (two-way) Health Monitor Networking
ZMD 44101 Complete PHY
Analog Digital Digital RX 1) Synchronization 2) Despreading 3) Demodulation 4) Digital Filtering Dedicated DSP Functions Digital TX 1) Spreading 2) Pulse Shaping
Thin HW-MAC
Application Specific Controller/Sensor
Analog Receiver
Airframing Error detection (CRC) Duty Cycle Host Interface SPI or parallel Registers
Additional MAC functions Protocol implementation Network support Upper layer functionality Application Interfaces (sensor)
PLL
Power Manager
Analog Transmitter
PLL RC-LPF
24MHz
32.768kHz
Copyright (c) 2005, ZMD AG
Data Sheet - March 2005
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The information furnished in this publication is preliminary and subject to changes without notice.
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
Table of Contents
1 2 Pin Diagram .................................................................................................................................... 3 General Device Specifications........................................................................................................ 4 2.1 2.2 2.3 2.4 3 3.1 3.2 4 4.1 4.2 4.2.1 4.3 5 5.1 5.2 5.3 5.4 5.5 6 7 8 Absolute Maximum Ratings ................................................................................................... 4 Recommended Operating Conditions .................................................................................... 4 D.C. Electrical Characteristics................................................................................................ 4 Digital I/O................................................................................................................................ 5 General................................................................................................................................... 5 Startup time ............................................................................................................................ 5 Overview ................................................................................................................................ 6 Serial Peripheral Interface (SPI) ............................................................................................ 7 SPI Configuration............................................................................................................... 7 Parallel Interface .................................................................................................................... 9 MAC control + status register............................................................................................... 10 MAC timing registers ............................................................................................................ 11 Other MAC registers............................................................................................................. 12 MAC header registers .......................................................................................................... 13 PHY registers ....................................................................................................................... 13
A.C. Electrical Characteristics ........................................................................................................ 5
Interfaces ........................................................................................................................................ 6
Registers ....................................................................................................................................... 10
Application circuit - external components .................................................................................... 14 ZMD44101 System Performance Summary ................................................................................. 15 System Description ....................................................................................................................... 16 8.1 8.2 8.2.1 8.3 8.3.1 8.4 8.5 8.6 8.7 8.8 General Block Diagram ........................................................................................................ 16 Receiver Chain..................................................................................................................... 17 RAGCL - AGC Level Register ......................................................................................... 18 Transmitter Chain................................................................................................................. 18 RTXM - Transmitter Mode Register................................................................................. 18 RF Phase Locked Loop........................................................................................................ 19 Reference Crystal Oscillator (24MHz).................................................................................. 20 Low Power Crystal Oscillator (32.768kHz)........................................................................... 21 CLKO - Clock Output Configuration ..................................................................................... 21 Power Management ............................................................................................................. 22 Package ............................................................................................................................... 23
9 10 11
Mechanical Specifications............................................................................................................. 23 9.1 List of abbreviations ...................................................................................................................... 25 References.................................................................................................................................... 25
Information is current as of publication date. Products conform to specification per the terms of the ZMD standard warranty. Production testing does not necessarily include testing of all parameters. Copyright (c) 2004, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
1
Pin Diagram
CLKO 36 37 MISO MOSI DA[7] DA[6] DA[5] DA[4] DA[3] DA[2] DA[1] DA[0] SCK
Figure 1.1 provides the pin layout for the ZMD44101 and Table 1.1 the description of the respective pins.
WR RD DVDD_3.3 DVSS DVDD ALE AVDD AVSS RTC1 RTC2 NC NC
25
24
SS IRQ GPD DVDD_3.3
ZMD44101 48 QFN (=MLF)
TOP VIEW
DVDD RSN DVDD NC NC AVDD LPF2
48
1 NC AVDD AVSS AVDD AVSS RFIO AVSS RFO AVDD XTAL1
13 12 XTAL2
LPF1
NC
Figure 1.1 - Pin Layout Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
NC NC AVDD AVSS AVDD AVSS RFIO AVSS RFO AVDD XTAL1 XTAL2 LPF1 LPF2 AVDD NC NC DVDD RSN DVDD DVDD_3.3 GPD IRQ SS
Pin Type
AVDD Ground AVDD Ground RF IO Ground RF Output AVDD Analog Input No connection No connection
Description
Pin No.
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Pin Name
MOSI MISO SCK DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7 CLKO WR RD DVDD_3.3 DVSS DVDD ALE AVDD AVSS RTC1 RTC2 NC NC
Pin Type
CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO CMOS IO
Description
SPI interface - master out, slave in SPI interface - master in, slave out SPI interface - serial clock Data address Data address Data address Data address Data address Data address Data address Data address
Analog power supply Analog ground RF power supply RF ground RF receiver input and transmitter output RF ground RF transmitter output Analog PLL power supply 24MHz crystal oscillator input
Analog Output 24MHz crystal oscillator output Analog Output Loop filter, charge-pump node Analog Input AVDD DVDD CMOS Input DVDD DVDD_3.3 CMOS IO Loop filter, VCO tune node Analog PLL VCO power supply No connection No connection Digital PLL power supply Asynchronous chip reset (low - active) Digital core 2.4V power supply (core and pre-driver) Digital IO 3.3V power supply (post-driver) Global Power Down (from external device)(h-active)
CMOS Output Clock (to external device) CMOS IO CMOS IO DVDD_3.3 Ground DVDD CMOS IO AVDD Ground Analog Input Write data address Read data address Digital IO 3.3V power supply (post-driver) Digital ground Digital core 2.4V power supply (core and pre-driver) Address latch enable Analog power supply Analog ground 32.768kHz crystal oscillator input
Analog Output 32.768kHz crystal oscillator output No Connection No Connection
CMOS Output Interrupt (to external device)(low active) CMOS IO SPI interface - slave select
Table 1.1 - Pin Descriptions
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
2
General Device Specifications
Electrical characteristics over full range of operating conditions, typical values are AVDD, DVDD = 2.4V, DVDD_3.3 = 3.3 V, Ta = 25C, unless otherwise noted.
2.1
Absolute Maximum Ratings
Caution: Operation beyond these values may cause permanent damage to the device or decrease in reliability. Note: Values are over free-air temperature unless otherwise noted. Parameter Analog Supply Voltage Digital Supply Voltage Digital IO Supply Voltage Input Voltage Output Voltage Analog Input Voltage Input RF Level Storage Temperature ESD Protection Symbol AVDD DVDD DVDD_3.3 Vi Vo Vana Pin Tstrg Vesd Min -65 Typ Max 3.5 3.5 4.6 6 4.6 3.5 20 150 2 Unit V V V V V V dBm C kV HBM (100pF, 1.5k) at CMOS IO at CMOS IO at analog IO Notes
2.2
Recommended Operating Conditions
Parameter Symbol AVDD DVDD DVDD_3.3 Ta fop Min 2.2 2.2 3.0 -40 860 Typ 2.4 2.4 3.3 +27 Max 2.7 2.7 3.6 +85 930 Unit V V V C MHz Industrial range 868.3MHz (EU), 902MHz to 928MHz (US) Notes
Analog Supply Voltage Digital Supply Voltage Digital IO Supply Voltage Ambient Temperature Frequency of Operation
2.3
D.C. Electrical Characteristics
Note: Values are for supply current.
Parameter Sleep mode (32kHz crystal and timer on) Idle mode (24MHz crystal on) Transmit mode Receive mode, synchronization Receive mode, normal
Symbol Idd Idd Idd Idd Idd
Min -
Typ 2 1 32 31 28
Max -
Unit A mA mA mA mA
Copyright (c) 2005, ZMD AG
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ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
2.4
Digital I/O
Symbol VIL VIH VOL VOH 2.4 Min -0.3 2 Typ Max 0.8 5.5 0.4 Unit V V V V Notes
Module CMOS Input CMOS Output
3
A.C. Electrical Characteristics
Electrical characteristics over full range of operating conditions, typical values are AVDD, DVDD = 2.4V, DVDD_3.3 = 3.3 V, TA = 25C, unless otherwise noted.
3.1
General
Symbol Pout Plow1 Plow2 Plow3 PSL Harmonics PN rEU rUS Pmin NF Pin,max IIP3 IIP2 LO leakage bandwidth fref BWLPF fres fcs N Min -3 Typ 0 -7 -14 -21 Max 3 Unit Note Transmitter dBm output power at 50 dBm low output power mode 1 dBm low output power mode 2 dBm low output power mode 3 dBm max. spurious emission=1st side lobe dBm dBm Standby radiation kBit/s Chip rate (EU) @ channel 0 kBit/s Chip rate (US) @ channel 1 to 10 Receiver dBm at packet error rate (PER) <1% dB dBm maximum usable input power dBm dBm dBm PLL MHz MHz crystal with 32pF Cload=32pF kHz LPF bandwidth Hz frequency resolution MHz channel spacing for IEEE 802.15.4 dBc (10...100) kHz offset
-30 -35 -57 300 600 -100 10 -20 -20 25 -57 860 24 300 732 2 -85 930
3.2
Startup time
Parameter Power on to idle mode Idle mode to Transmitter ready Idle mode to Receiver ready Receiver to Transmitter turnaround Transmitter to Receiver turnaround Time 1.0 (typical) 0.18 0.2 0.2 0.2 Unit ms ms ms ms ms
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
4 4.1
Interfaces Overview
SPIconfig[5:0] SPItx[7:0] SPIstart SPIrx[7:0] Reg. Bank SPI MOSI MISO SCK SS
Digital Core
TX FIFO 128x8
Interface ALE RD WR DA[7:0] IRQ GPD
RX FIFO 256x8
Parallel
Figure 4-1: Interface Block Diagram The ZMD44101 provides a parallel interface and an SPI to access the internal register bank, the TX and the RX FIFO. Additionally it has a IRQ output and a dedicated global power down (GPD) input. By default both interfaces the parallel and the SPI as slave are available. For proper operation the unused interface shall be disabled. The parallel interface is disabled by setting RD,WR, and ALE to high, putting the DataAddress[7:0] bus into High-Z state. The SPI is disabled by setting SS to high. The SPI can also be configured as master. In the master setup is behaves like a remote interface which can be controlled by the external microcontroller via the ZMD44101 parallel interface and some SPI control register in the register bank.
Copyright (c) 2005, ZMD AG
Page 6 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
4.2
4.2.1
Serial Peripheral Interface (SPI)
SPI Configuration
The SPI is configured via the SPIconfig (R/W ) register. A standard based SPI is used by default in slave mode. Certain registers can switch the interface to master mode to work with another slave. In that case the parallel microcontroller interface is used to control the ZMD44101. The interface provides the standard lines MISO, MOSI, SCK and SS. For Write Access the first bit of the first byte on MOSI has to be `0'. For Read Access the first bit of the first byte written to MOSI has to be `1'. SS (Slave Select) has to be `0' when accessing the ZMD44101 through the SPI. The ZMD44101 uses a data transfer protocol allowing single and multiple byte read/write access. All bytes are transmitted with the MSB first and the LSB last. The protocol always starts by writing 2 bytes to the SPI slave via the MOSI line. The MSB of the first byte is the read/write indicator. A high bit stands for read access and a low bit for write access. The read/write bit is followed by the length[6:0] descriptor N. It controls the length of the data frame D0[7:0] to DN-1[7:0]. N hast to be in a range 1 to 127.The second byte is the address[7:0]. For TX/RX FIFO access the address are 0x80 and 0x81 respectively. Note that the TX FIFO only allows write access and the RX FIFO read access. In the case of register bank access a number of N bytes is read starting from address[7:0] up to address[7:0]+(N-1). In the case the FIFO locations 0x80 or 0x81 are within this range they are skipped and the read/write access is continued at location 0x82. For write access the address[7:0] byte is followed by the data frame D0[7:0] to DN-1[7:0]. In figure 4-2 the slave select signal SS is low during the complete write transfer. However it is also allowed to insert SS high gaps between each byte. In the read access protocol the data frame is shifted out by the slave on the MISO line. Before each data byte a SS high gap is required. Similar to the write access a SS high gap can be inserted before the address[7:0] byte. Timing parameters are listed in the following table. Parameter tcp tsc tss Description min SCK clock period SS low to SCK active edge SS high pulse with 0.50 s 0.25 s 1.00 s US mode max min 1.00 s 0.50 s 2.00 s EU mode max
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
write access: SCK W MOSI tcp SS tsc read access: SCK R MOSI tcp MISO D0[7:0] tcp SS tsc tss D1[7:0] Length[6:0] (N) A[7:0] Length[6:0] (N) A[7:0] D0[7:0] DN-1[7:0]
...
...
DN-1[7:0]
...
Figure 4-2: Transfer Protocol (SPI Slave Mode), CPHA=0 CPOL=0
Copyright (c) 2005, ZMD AG
Page 8 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
4.3
Parallel Interface
The parallel interface consists of the bi-directional DataAddress[7:0] bus and the control inputs read (RD), write (WR) and address latch enable (ALE). The direction of the DA[7:0] bus is controlled by the RD input. If RD is high DA[7:0] are in input mode. Setting RD low turns DA[7:0] into output direction. The timing diagram for read and write access is shown below.
write access: DA[7:0] Address tad ALE tas WR tds RD read access: DA[7:0] Address X Read Data tdh tah Write Data
ALE tas WR tar RD trvd tzd tah
Figure 4-2: Parallel Interface Read/Write Access Timing parameters are listed in the following table. Parameter tas tah tad tds tdh tar tzd trvd Description min address setup time address hold time address to data time data setup time data hold time address to RD low time high-z to data time read low to valid data 0 200 ns 0 0 300 us 0 0 10 ns 400 us US mode max min 0 200 ns 0 0 600 us 0 0 10 ns 800 us EU mode max
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
5
Registers
The ZMD44101 has several registers for MAC and PHY functional support. The register description shall give a brief overview only. A more detailed description can be found in the users manual. The registers are accessible through the two interface ports. The Hardware-MAC registers provide a great advantage for system implementation in comparison to a MAC implementation in a microcontroller only. Especially many system timing critical functions are implemented in the ZMD44101. Most registers can be referred to in the IEEE802.15.4 standard.
5.1
Addr 8'hE0 8'hE1 8'hE2 8'hE3 8'hE4 8'hE5 8'hE6 8'hE7 8'hE8
MAC control + status register
Register name IRQreason IRQmask1 IRQmask2 IRQmask3 SPIconfig SPIstart SPItx SPIrx ClkOutConfig bits 8 8 8 7 6 1 8 8 8 5 4 6 4 2 4 7 8 8 4 3 4 type RW RW RW RW RWI RWS RW R RW RW RW RW RW RW R R R R R R R default 0 8'h00 8'h00 7'h00 6'h20 0 0 0 8'h29 5'h1F 4'h2 6'h1A 4'h1 0 0 0 0 0 0 0 0 description interrupt reason interrupt mask[7:0] interrupt mask[15:8] interrupt mask[22:16] SPI configuration register SPI start (master mode) SPI transmit byte (master mode) SPI receive byte (master mode) CLKO pad configuration (def: normal mode = 24Mhz/4, sleep mode = 32.768kHz) MAC control command used by firmware to control the HW-MAC fsm transitions this control word is cleared by the internal logic after it was fetched 8'hF3 MAC transmit mode configuration MAC rx mode configuration MAC beacon track mode configuration MAC scan mode (ed, passive, active, orphan) MAC operating mode status register MAC transmit status register MAC rx status register MAC scan status register MAC beacon track status register MAC auto beacon tx status register MAC tx/rx fifo status register
8'hF0 macControl 8'hF1 8'hF2 8'hF3 8'hF4 8'hF5 8'hF6 8'hF7 8'hF8 8'hF9 8'hFA 8'hFB macTxConfig macRxConfig macBcTrConfig macScanMode macOpMode macTxStatus macRxStatus macScanStatus macBcTrStatus macAutoBcTxStatus macFifoStatus
Copyright (c) 2005, ZMD AG
Page 10 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
5.2
Addr 8'hC0 8'hC1 8'hC2 8'hC9 8'hDA 8'hCB 8'hCC 8'hCD 8'hCE 8'hCF 8'hD0 8'hD1 8'hD2 8'hD3
MAC timing registers
Register Name T_RxDefer1 T_RxDefer2 T_RxDefer3 T_ScanDuration1 T_ScanDuration2 T_ScanDuration3 T_BeaconInterval1 T_BeaconInterval2 T_BeaconInterval3 Td_BeaconInterval T_BeaconScanDuration1 T_BeaconScanDuration2 T_BeaconScanDuration3 T_BeaconScanStart1 bits 8 8 8 8 8 8 8 8 8 4 8 8 8 8 3 8 8 8 8 3 4 type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW default 8'h00 8'h00 8'h00 8'h00 8'h78 8'h00 8'h00 8'h78 8'h00 4'h4 8'h00 8'hF0 8'h00 8'h0A 3'h0 8'h00 8'h00 8'h00 0 0 4'h0C description rx defer time [7:0] rx defer time [15:8] rx defer time [23:16] scan duration (960*2^5) [7:0] scan duration (960*2^5) [15:8] scan duration (960*2^5) [23:16] beacon interval (960*2^5) [7:0] beacon interval (960*2^5) [15:8] beacon interval (960*2^5) [23:16] T delta beacon interval generate IRQ 2^Td_BeaconInterval before next beacon beacon scan duration (960*2^6) [7:0] beacon scan duration (960*2^6) [15:8] beacon scan duration (960*2^6) [23:16] beacon scan start (symbols before beacon interval end) (10) [7:0] beacon scan start (symbols before beacon interval end) (10) [10:8] sleep time [7:0] sleep time [15:8] sleep time [23:16] superframe timing deviation between RFD and FFD [7:0] superframe timing deviation between RFD and FFD [10:8] used as additional guard time in CAP/GTS check superframe timing alignment order the RFD superframe timer is aligned to the estimated FFD timing every 60*2^SFalignOrder symbols (12)
8'hD4 T_BeaconScanStart2 8'hD5 8'hD6 8'hD7 8'hD8 8'hD9 T_Sleep1 T_Sleep2 T_Sleep3 Tdelta1 Tdelta2
8'hDA SFalignOrder
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
5.3
Addr 8'h9D 8'hA0 8'hA1 8'hA2 8'hA3 8'hA6 8'hA7 8'hA8 8'hA9 8'hAA 8'hAB 8'hAC 8'hAD 8'hAE 8'hAF 8'hB0 8'hB1 8'hB2 8'hB3 8'hB4 8'hB5 8'hB6 8'hB7 8'hBE 8'hBF 8'h75 8'h76 8'h77 8'h78
Other MAC registers
Register name msduLengthTx mhrFc1Rx mhrFc2Rx mhrSquNbRx mpduLengthRx macFramePend macSuperframeOrder macCAPend macGTSstart macGTSlength macTotalTimeFFD1 macTotalTimeFFD2 macTotalTimeFFD3 macTotalTimeRFD1 macTotalTimeRFD2 macTotalTimeRFD3 macCurrentSymbolTime1 macCurrentSymbolTime2 macCurrentSymbolTime3 MacCurrent Slot macBeaconRxTime1 macBeaconRxTime2 macScanED macMaxLostBeacons macSyncLoss CRCfail1 CRCfail2 FrameRxCount1 FrameRxCount2 bits 7 8 8 8 7 6 4 4 4 4 8 8 8 8 8 8 8 8 8 4 8 5 8 4 4 8 6 8 6 type RW R R R R RW RW RW RW RW R R R R R R R R R R R R R RW R R R R R default 0 0 0 0 0 0 5 15 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 4 0 0 0 0 description MAC payload (msdu) length (Tx) MAC header frame control byte 1 (Rx - last received frame) MAC header frame control byte 2 (Rx - last received frame) MAC header sequence number (Rx - last received frame) mpdu length (Rx - last received frame) number of frames pending in Rx FIFO queue, reset by software MAC superframe order (SO) last slot in CAP 1st slot of the GTS GTS length in slots (zero no GTS) current totaltime [7:0] (FFD mode) in multiple of 32kHz clock current totaltime [15:8] (FFD mode) current totaltime [23:16] (FFD mode) current totaltime [7:0] (RFD mode) current totaltime [15:8] (RFD mode) current totaltime [23:16] (RFD mode) current superframe time [7:0] current superframe time [15:8] current superframe time [23:16] current slot timestamp[7:0] of the last received beacon timestamp[12:8] of the last received beacon maximum ED value from the ED scan number of max lost beacons before a SyncLoss is indicated number of lost beacons number of CRC failures [7:0] number of CRC failures [13:8] number of received frames [7:0] number of received frames [13:8]
Copyright (c) 2005, ZMD AG
Page 12 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
5.4
Addr. 8'h82 8'h83 8'h84 8'h85 8'h86 8'h87 8'h88 8'h89 8'h8A 8'h8B 8'h8C 8'h8D 8'h8E 8'h8F 8'h90 8'h91 8'h92 8'h93 8'h94 8'h95 8'h96 8'h97 8'h98 8'h99 8'h9A 8'h9B 8'h9C
MAC header registers
Register name mhrFc1Tx mhrFc2Tx mhrSquNbTx mhrDstPanId1Tx mhrDstPanId2Tx mhrDstAddr16_1Tx mhrDstAddr16_2Tx mhrDstAddr64_1Tx mhrDstAddr64_2Tx mhrDstAddr64_3Tx mhrDstAddr64_4Tx mhrDstAddr64_5Tx mhrDstAddr64_6Tx mhrDstAddr64_7Tx mhrDstAddr64_8Tx mhrSrcPanId1Tx mhrSrcPanId2Tx mhrSrcAddr16_1Tx mhrSrcAddr16_2Tx mhrSrcAddr64_1Tx mhrSrcAddr64_2Tx mhrSrcAddr64_3Tx mhrSrcAddr64_4Tx mhrSrcAddr64_5Tx mhrSrcAddr64_6Tx mhrSrcAddr64_7Tx mhrSrcAddr64_8Tx bits 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 description MAC header frame control byte1(low byte) (Tx) MAC header frame control byte2(high byte) (Tx) MAC header sequence number (Tx) MAC header dest. pan identifier byte1(low byte) (Tx) MAC header dest. pan identifier byte2(high byte)(Tx) MAC header dest. 16bit address byte1(low byte) (Tx) MAC header dest. 16bit address byte2(high byte) (Tx) MAC header dest. 64bit address byte1(low byte) (Tx) MAC header dest. 64bit address byte2 (Tx) MAC header dest. 64bit address byte3 (Tx) MAC header dest. 64bit address byte4 (Tx) MAC header dest. 64bit address byte5 (Tx) MAC header dest. 64bit address byte6 (Tx) MAC header dest. 64bit address byte7 (Tx) MAC header dest. 64bit address byte8(high byte) (Tx) MAC header source pan identifier byte 1(low byte) (Tx) MAC header source pan identifier byte 2(high byte (Tx) MAC header source 16bit address byte 1(low byte) (Tx) MAC header source 16bit address byte 2 (Tx) MAC header source 64bit address byte 1 (Tx) MAC header source 64bit address byte 2 (Tx) MAC header source 64bit address byte 3 (Tx) MAC header source 64bit address byte 4 (Tx) MAC header source 64bit address byte 5 (Tx) MAC header source 64bit address byte 6 (Tx) MAC header source 64bit address byte 7 (Tx) MAC header source 64bit address byte 8(high byte) (Tx)
5.5
Addr
PHY registers
register name bits 8 6 8 Name phyCurrentChannel Register Transmitter Mode Register AGC Level Register Remarks RF channel selection Transmitter baseband filtering, output port select, and PA output level controls Indicates AGC level in closed loop mode and sets AGC gain in open loop mode
8'h00 RPCC 8'h05 RTXM 8'h0E RAGCL
The system description in paragraph 8 gives information about the registers in the PHY. Many more registers can be accessed and programmed/read but are not essential for typical applications. All PHY registers are written through MAC commands as defined in the IEEE802.15.4 standard. They can be overridden. All PHY registers are read and write capable. Every register can be written to and read from at any time during operation by the microcontroller through either the parallel or SP Interface. A detailed description of all register will be available as an application note.
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
6
Application circuit - external components
The ZMD44101 requires very few external components allowing for a small module form factor and low Bill of Material costs. Figure 6.3 depicts which components are required in a typical application. Aside from these components only a microcontroller, with it's external components, is needed. This microcontroller has to maintain and control the application specific software dependent functions as defined by the ZigbeeTM standard. The standard microcontroller interfaces are described in paragraph 4.3.
SPI 3.3volt
C11
36 CLKO MISO DA[7] DA[6] DA[5] DA[4] DA[3] DA[2] DA[1] DA[0] SCK 37 WR RD DVDD_3.3 DVSS DVDD
25 MOSI SS 24 IRQ GPD DVDD_3.3 DVDD
RESET Interrupt Power Down
11 Microcontroller Interface
ALE AVDD AVSS RTC1
ZMD44101
RSN DVDD NC NC AVDD LPF2 LPF1 13 XTAL1 XTAL2 AVDD
2.4volt
C10
C1
Q1
RTC2 NC
C2
48 NC NC 1 NC
Figure 6.1 - external components in a typical ZMD44101 application component C1 C2 C3 C4 C5 C6 C7 value 15pF, 5%, SMD 15pF, 5%, SMD 22pF, 5%, SMD 43pF, 5%, SMD 43pF, 5%, SMD 5.6pF, 5%, SMD 220pF, 5%, SMD component C8 C10 C11 R1 R2 Q1 Q2 value 15pF, 5%, SMD >100uF II 100nF, 6.3v, decoupling >100uF II 100nF, 6.3v, decoupling 12kOhm, 5%, SMD 3.9kOhm, 5%, SMD 32.768kHz, watch crystal type 24MHz, 40ppm
AVDD
C3
AVDD
AVSS
AVSS
AVSS
RFIO
RFO
12
R2 Q2 R1
C4
C5
C6
C7
C8
Copyright (c) 2005, ZMD AG
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ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
7
ZMD44101 System Performance Summary
Parameter Operational Specifications Value
Note: Simulated system performance based on IEEE 802.15.4 standard.
Supply Voltage Digital IO Voltage Temperature Range Frequency of Operation Typical Supply Current (TX) Typical Supply Current (RX-synchronization) Typical Supply Current (RX-normal) Typical Supply Current (sleep mode)
+2.2V to +2.7V (typical +2.4V) +3.0V to +3.6V (typical +3.3V) -40C to +85C 868MHz to 870MHz (EU) and 902MHz to 928MHz (US) 32mA 31mA 28mA 2A
System Specifications
Standard Basis Spreading Technique Modulation Type Data Rate Burst PN Code Processing Gain Chip Rate RF Bandwidth RF Channel Spacing Overall Crystal Accuracy IEEE 802.15.4/D18 Compliant Direct Sequence Spread Spectrum (DSSS) Binary Phase Shift Keying (BPSK) 20kBits/s (EU) and 40kBits/s (US) 15-chip m-sequence 12dB 300kBit/s (EU) and 600kBit/s (US) 600kHz (EU) and 1200kHz (US) 2MHz (IEEE 802.15.4 compliant) 40ppm
Architecture
Receiver (RX) Transmitter (TX) Phase Locked Loop (PLL) Direct Down-Conversion Direct Up-Conversion Sigma-Delta Fractional-N
Block Specifications
RF_PLL Frequency Resolution TX Output Power TX Spurious Emissions RX Sensitivity RX Maximum Usable Input Level RX Selectivity/Blocking Performance 732Hz 0dBm (to 50) ETSI (EN 300 220) and FCC (Part 15) compliant -100dBm@PER<1% -20dBm IEEE 802.15.4 Compliant + ETSI RX Class 2
General Parameters
Package ESD Protection Interface External Components Process Technology 48-pin QFN (=MLF SPI and Parallel 24MHz & 32.768kHz XTAL, PLL loop filter (RC), Antenna, Microcontroller 0.25m CMOS
TM
MicroLeadFrame)
>2kV (Human Body Model - HBM)
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
8 8.1
System Description General Block Diagram
I
LNA
LP Filter
AGC with LPF ADC Gain
Q
ADC
PA
Mixer DAC
900MHz
TX
Channel 24MHz PFD XTAL OSC Frequency Doubler 48MHz
Master Bias
RF PLL
XTAL OSC
LPF 24MHz 32.768kHz
Figure 8.1 - Integrated Analog PHY Layer block diagram
Copyright (c) 2005, ZMD AG
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Digital Part Digital Part
POR
RX
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
PHY TX TX Data Path - phy frame - byte to bit - diff. encode - spreading - pulse shape
MAC TX CRC
Ack Frame TX FIFO/ RX FIFO(2) Parallel
MAC Framer
PHY TX Control
Beacon/Sync Timing Scan Timing
RTC Inter face
Power Control
MAC Control Clock Control
CSMA Symbol Timer
Reg. Bank
SPI
MAC Control
GTS Timing
IRQ
PHY RX Control
GPD
RX Data Path - ED - carrier sense - acquisition - notch - down convert - despread - diff. demod - bit to byte PHY RX
CRC
Bad Frame Counter
PER/BER
Header Decode MAC RX
AckReq, SeqNum, FrameType
RX FIFO(1)
Figure 8.2 - Integrated digital PHY and MAC Layer block diagram
8.2
Receiver Chain
The receiver of the ZMD44101 uses a direct-conversion architecture (Zero-IF architecture). The receiver path consists of a 900MHz low-noise amplifier (LNA) and a mixer, followed by the analog baseband. It contains multi-stage programmable gain amplifiers, low-pass filter sections and Analog-todigital converters (ADC). All remaining functions are carried out in the digital domain including synchronization, de-spreading and demodulation as well as the AGC loop control. To extend the dynamic range further, the LNA and mixer gain can be adjusted in the AGC loop. In normal operation mode, the user or the MAC starts the reception using the default register values. All control signals (timing, power-down) are set automatically. One receiver register setting can be important for receiver operation (RAGCL). This is described in paragraph 8.2.1. Besides this register there are registers which are used in both, transmit and receive mode.
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
8.2.1 RAGCL - AGC Level Register
Bit7 Bit6 Bit5 1 Bit4 1 Bit3 1 Bit2 1 Bit1 1 Bit0 1 0 1 1=gain high, 0=gain low
The register can be used to read the AGC level back to the microcontroller at any time during receiver operation. This way information about the signal strength can be derived by the microcontroller. The high gain default value (hex7F) together with the digital peak detection function ensures fast settling time by reducing the gain in steps to a usable signal level for the digital signal processing inside the ZMD44101.
8.3
Transmitter Chain
A direct-conversion architecture is used for the transmitter of the ZMD44101. The design is fully differential. Only the Power Amplifier (PA) output is single-ended. No external balun is required. In normal operation mode, the user or the MAC starts the transmission using the default register values. All control signals (timing, power-down) are set automatically. Optionally two default register settings of the transmitter can be changed by writing to the Transmitter Mode Register (RTXM). By default, the PA drives 0dBm (1mW) to a 50 Ohm off-chip load. This output power can be changed between 0dBm and -21dBm.
8.3.1 RTXM - Transmitter Mode Register
Bit7 default 0 dBm output power -7 dBm output power -14 dBm output power -21 dBm output power Normal operation Carrier only modulation Constant '0' data transmit RFIO is output RFO is output 0 0 0 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 0 0 0 0 0 Bit5 0 0 0 1 1 X X X X X Bit4 0 0 1 0 1 X X X X X Bit3 0 X X X X X X X 0 1 Bit2 0 X X X X 0 0 1 X X Bit1 0 X X X X 0 1 0 X X Bit0 0 X X X X 0 0 0 X X
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ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
TX-RX-Switch Configuration
RXIO LNA
Furthermore, by default the receiver input and the transmitter output use the same pin (RFIO). The integrated antenna switch disconnects the respective components in transmit and receive mode. By changing bit3 in the RTXM register, the transmitter uses RFO as the output pin. This allows to use an external Power Amplifier for higher output power and extended range (see left figure). The antenna has to be connected via an external 22pF capacitor.
RFIO
TXIO
PA
TXO
RFO
8.4
RF Phase Locked Loop
A fractional-N Phase Locked Loop (PLL) architecture is used. All functions are integrated on chip except for the loop filter. The external loop filter circuitry is depicted in Figure 8.3. The 24MHz crystal (see paragraph 8.5) provides the reference frequency for both the EU- and US-bands.
LP_CP 3.9k 5% 12k 5% LP_VCO
5.6pF 5%
220pF 5%
15pF 5%
Figure 8.3 - PLL-Loop filter In normal operation mode, the user sets the frequency channel of the RF PLL prior to transmission or reception. All control signals (timing, power-down) are set automatically by writing to the phyCurrentChannel register (RPCC), but can be overwritten for non-standard applications. The data rate (EU: 20kBit/s and US: 40kBit/s) is adjusted automatically according to the selected channel. The channel numbers are defined by the IEEE 802.15.4 standard. Figure 8.4 illustrates the channel allocation in the 900MHz band. Table 8.1 depicts the RPCC programming in the ZMD44101.
Channel 0
Channels 1-10
2 MHz
868.3 MHz
902 MHz
928 MHz
Figure 8.4 - Channel allocation in the 900MHz band
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
Band
Channel select (RPCC Reg.) as per IEEE802.15.4 European 0 USA 1 USA 2 USA 3 USA 4 USA 5 USA 6 USA 7 USA 8 USA 9 USA 10
Channel (MHz) 868.3 906 908 910 912 914 916 918 920 922 924
Channel (bin) (RPLC1/2 Reg.) 0010110111011101 1100000000000001 1101010101010101 1110101010101011 0000000000000000 0001010101010101 0010101010101011 0100000000000001 0101010101010101 0110101010101011 1000000000000001
Channel (dec) 11741 49153 54613 60075 0 5461 10923 16385 21845 27307 32769
SEL_SUBBAND (RPLM Reg.) 01 10 10 10 11 11 11 11 11 11 11
Table 8.1 - Channel select register programming according to the IEEE 802.15.4 standard
8.5
Reference Crystal Oscillator (24MHz)
A two (2) pin Pierce oscillator with on-chip biasing resistor is designed to provide the necessary reference frequency at 24MHz. This frequency is used for digital clock supply, timing calculations as well as for the PLL that generates the RF carrier frequency. For the receive modes the internal circuitry doubles the reference frequency in order to achieve the digital processing speed during code acquisition. This oscillator is only active in Idle, Transmit and Receive power modes. The user can also provide an external 24MHz clock reference on XTAL1. This external clock has to have 24MHz at a duty cycle of 1:1 and an accuracy of 40ppm. Provided this case no 24MHz crystal is required between XTAL1 and XTAL2 and XTAL2 is not connected. When the internal oscillator is used C4 and C5 are required as load capacitors for the parallel resonance crystal. The values C4 and C5 are different for any specific environment. The overall load capacitance is composed of the actual values of C4 and C5 as well as the parasitic values of the PCB layout and the internal parasitic capacitance of the ZMD44101, which is 0.65pF on each pin. The total load capacitance has to match the recommended typical load capacitance provided by the crystal manufacturer. For a recommended 97SMX240 22B crystal (SMI) the load capacitance is 22pF0.5%. Any deviation on this system part will result in large deviation on the carrier frequency and output spectrum. This clock is available for external use on Pin 36, CLKO. It can be used to support a microcontroller. During power-down and sleep mode the microcontroller clock is switched to 32.768kHz or to selectable fractions of 32.768kHz for reduced current consumption. This ensures the microcontroller has a clock signal during power-down and therefore can correctly wake up from the power-down state. During all other states the 24Mhz clock or selectable fractions of 24MHz can be used on CLKO.
C4 24MHz C5 XTAL2 XTAL1
Figure 8.5 - 24Mhz crystal oscillator - external components
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Page 20 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
8.6
Low Power Crystal Oscillator (32.768kHz)
The 32.768kHz crystal oscillator is designed for extreme low power operation as it always runs when power is applied to the device. The oscillator provides the time reference for the on-chip real time clock. The oscillator utilizes an amplitude controlled two (2) pin Pierce oscillator with on-chip biasing resistor. The same as described for the 24MHz oscillator in paragraph 8.5 is valid for the load capacitance.
RTC1
32.768kHz
RTC2
Figure 8.6 - 32.768khz crystal oscillator - external components This clock is available for external use on Pin 36, CLKO. It can be used to support a microcontroller. During power-down and sleep mode the microcontroller clock is switched to 32.768kHz or to selectable fractions of 32.768kHz for reduced current consumption. This ensures the microcontroller has a clock signal during power-down and therefore can correctly wake up from the power-down state.
8.7
CLKO - Clock Output Configuration
This register is part of the MAC control and status registers. The clock on the CKLO pin can be configured according to the following table for external microcontroller clock support. Pin36 can directly drive a clock input up to 4mA. ClkOutConfig[7:6] value 0 1 2 3 RtcDiv(M) 1 2 4 8 ClkOutConfig[5:4] Clk24Div(N) 1 2 4 8 ClkOutConfig[3:2] NormalModeClk OFF 32k/M 24M/N ClkOutConfig[1:0] SleepModeClk OFF 32k/M 24M/N
The table is to be read as follows. Example default: The ClkOutConfig(@default)=8'b00101001, compares to "0,2,2,1". That means: M=1, N=4, during normal mode (everything but not sleep or GPD) CLKO is 24MHz/4=6MHz, and during sleep mode CLKO is 32.768kHz.
Page 21 of 26
Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
8.8
Power Management
The ZMD44101 has five different modes of power management. These modes are user configurable and controlled by the external microcontroller. The power modes are as follows: * Tx/Rx: Tx or Rx is active. * IDLE: Tx/Rx are powered down but the 24MHz crystal oscillator remains on. * SLEEP: All circuits are switched off except the 32.768kHz RTC for accurate time reference. Power consumption is reduced to 2A (typical). * POWER DOWN: The ZMD44101 enters into power down by setting the Global Power Down (GPD) function. * POWER OFF: The supply voltage is switched off externally. The ZMD44101 has a Power On Reset (POR) function. NOTE: The ZMD44101 contains internal master bias circuitry. No adjustments or external circuitry are required for accurate operation.
Copyright (c) 2005, ZMD AG
Page 22 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
9 9.1
Mechanical Specifications Package
48pin QFN Package
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Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
Dim A A1 b D E D1 E1 e L L1 L2 P aaa ccc
Min 0.80 0.18
Typ 0.203 Ref 0.25 7.00 BSC 7.00 BSC
Max 1.00 0.30
Notes
Applies to metallized terminal and is measured between 0.25mm and 0.30mm from terminal tip.
5.04 5.04 0.43 0.30 0.50 BSC 0.53 0.40 45o BSC 0.15 0.10
5.24 5.24 0.63 0.10 0.50 Represents terminal full back from package edge up to 0.1mm is acceptable.
Notes: 1. Dimensions and tolerances conform to ASME Y14.5M-1994 2. All dimensions are in millimeters. Angles are in degrees. 3. Co-planarity applies to the exposed head slug as well as the terminal. 4. Radius in terminal is optional.
Copyright (c) 2005, ZMD AG
Page 24 of 26
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
10 List of abbreviations
ADC AES AGC BER BPSK CMOS CRC CSMA DAC dB DSSS ED ESD ETSI EU FCC FIFO GPD GTS IEEE IF Analog-to-Digital Converter Advanced Encryption Standard Automatic Gan Control Bit Error Rate Binary Phase Shift Keying Complementary Metal Oxide Silicon Code Redundancy Check Carrier Sense Multiple Access Digital-to-Analog Converter Decibel Direct Sequence Spread Spectrum Energy Detection Electrostatic Discharge European Telecommunications Standards Institute Europe Federal Communications Commission First In First Out General Power Down Guaranteed Time Slot Institute of Electrical and Electronics Engineers Intermediate Frequency IRQ ISM kbit/s kHz LNA LoS LP Filter MAC MISO MOSI MHz MLF PER PHY PLL QFN RF RTC RX SPI SS TX US XTAL Interrupt request Industrial- Scientific Medical Kilobit per second Kilohertz Low Noise Amplifier Line of sight Low Pass Filter Medium Access Controller Master-In-Slave-Out, Master-Out-Slave-In Megahertz Micro Lead Frame Packet Error Rate Physical (Layer) Phase Locked Loop Quad Flat Pack Radio Frequency Real Time Clock Receiver Serial Peripheral Interface Slave-Select (refers to CS=Chip Select) Transmitter United States Crystal
11 References
* IEEE 802.15.4-2003 Standard: "IEEE Standard for Part 15.4: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low Rate Wireless Personal Area Networks (LRWPANs)". Download: http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf * ETSI EN 300 220-1 V1.3.1 (2000-09) * FCC Part 15, December 18 2001
Page 25 of 26
Copyright (c) 2005, ZMD AG
ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver
PRELIMINARY - March 2005
The information furnished here by ZMD is believed to be correct and accurate as of the publication date. However, ZMD shall not be liable to any third party for any damages, including but no limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the technical data. No obligation or liability to any third party shall arise or flow out of ZMD's rendering technical or other services.
For Further Information
ZMD Phone: 858-674-8433 Fax: 858-674-8071 e-mail: wireless@zmda.com
ZMD 15373 Innovation Drive Suite 115 San Diego, CA 92128 http://www.zmd.biz
ZMD AG Grenzstrasse 28 D-01109 Dresden
Tel.: +49 351 8822 928 Fax: +49 351 8822 666
Products sold by ZMD are covered exclusively by the ZMD standard warranty, patent indemnification, and other provisions appearing in ZMD standard "Terms of Sale". Testing and other quality control techniques are used to the extent ZMD deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ZMD makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the Materials pertaining to ZMD products, or regarding the freedom of any products described in the Materials from patent and/or other infringement. ZMD reserves the right to discontinue production and change specifications and prices, make corrections, modifications, enhancements, improvements and other changes of its products and services at any time without notice. ZMD products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional mutually agreed upon processing by ZMD for such applications. ZMD assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using ZMD components.
Print date: 30.03.2005 11:29
Copyright (c) 2005, ZMD AG
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